H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 247

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Bit 4—Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A.
Bits 3 to 0—Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an
interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the
DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the transfer counter
and address register again, and then setting the DTE bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B
transfer end interrupt.
Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A
transfer end interrupt.
Bit 5
DTE0B
0
1
Bit 4
DTE0A
0
1
Bit 3
DTIE1B
0
1
Bit 2
DTIE1A
0
1
Description
Data transfer disabled
Data transfer enabled
Description
Data transfer disabled
Data transfer enabled
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
Description
Transfer end interrupt disabled
Transfer end interrupt enabled
Rev. 3.00 Sep 15, 2006 page 213 of 988
Section 7 DMA Controller (DMAC)
REJ09B0330-0300
(Initial value)
(Initial value)
(Initial value)
(Initial value)