H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 880

no-image

H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Appendix B Internal I/O Register
BCRL—Bus Control Register L
Rev. 3.00 Sep 15, 2006 page 846 of 988
REJ09B0330-0300
Bit
Initial value
Read/Write
:
:
:
BRLE
Bus Release Enable
R/W
0
1
7
0
BREQO Pin Enable
External bus release is disabled
External bus release is enabled
0
1
BREQOE
R/W
BREQO output disabled
BREQO output enabled
6
0
Reserved
Only 0 should be written to this bit
R/W
5
1
LCAS Select
Write 0 to this bit when using the DRAM interface
LCASS
R/W
4
1
DACK Timing Select
0
1
DDS
R/W
3
1
When DMAC single address transfer is performed in
DRAM space, full access is always executed DACK
signal goes low from T
Burst access is possible when DMAC single address
transfer is performed in DRAM space DACK signal
goes low from T
H'FED5
Reserved
Only 1 should be written to this bit
R/W
2
1
Write Data Buffer Enable
0
1
c1
or T
WDBE
Write data buffer
function not used
Write data buffer
function used
R/W
1
0
r
2
or T
cycle
WAIT Pin Enable
0
1
1
cycle
WAITE
Wait input by WAIT
pin disabled
Wait input by WAIT
pin enabled
R/W
0
0
Bus Controller

Related parts for H8S-2350