H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 347

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

8.3.8
Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
DTC vector
address
Chain Transfer
Register information
start address
Figure 8.9 Chain Transfer Memory Map
Register information
Register information
CHNE = 1
CHNE = 0
Section 8 Data Transfer Controller (DTC)
Rev. 3.00 Sep 15, 2006 page 313 of 988
REJ09B0330-0300
Destination
Destination
Source
Source