H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 305

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 7.26 shows an example of DREQ level activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Address bus
DMA control
Figure 7.26 Example of DREQ
Channel
DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
The DMA cycle is started.
Acceptance is resumed after the dead cycle is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Minimum of 2 cycles
Bus release
[1]
Request
Idle
[2]
Read
[3]
Request clear period
Transfer
DREQ
DREQ
DREQ Level Activated Block Transfer Mode Transfer
source
DMA
read
Write
1 block transfer
Acceptance resumes
DMA
write
destination
Transfer
Dead
Minimum of 2 cycles
[4]
DMA
dead
Request
Idle
[5]
release
Rev. 3.00 Sep 15, 2006 page 271 of 988
Bus
Read
[6]
Section 7 DMA Controller (DMAC)
Transfer
Request clear period
source
DMA
read
Write
1 block transfer
destination
Transfer
DMA
write
Dead
Acceptance resumes
REJ09B0330-0300
DMA
dead
[7]
release
Idle
Bus