H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 303

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Figure 7.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin
high level sampling has been completed by the time the DMA dead cycle ends, acceptance
resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this
operation is repeated until the transfer ends.
Figure 7.24 Example of DREQ
[1]
[2] [5]
[3] [6]
[4] [7]
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
Address bus
DMA control
Channel
DREQ
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ,
and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle; DREQ pin high level sampling on the rising edge of
When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle
is completed.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Bus release
Minimun of 2 cycles
[1]
Request
Idle
[2]
DREQ
DREQ
DREQ Pin Falling Edge Activated Block Transfer Mode Transfer
Read
Request clear period
[3]
Transfer
DMA
read
source
Write
1 block transfer
Acceptance resumes
DMA
write
destination
Transfer
Dead
Minimun of 2 cycles
[4]
Request
DMA
dead
Idle
[5]
release
Rev. 3.00 Sep 15, 2006 page 269 of 988
Bus
Read
[6]
Section 7 DMA Controller (DMAC)
Request clear period
Transfer
DMA
source
read
Write
1 block transfer
destination
starts.
DMA
Transfer
write
Dead
Acceptance resumes
REJ09B0330-0300
DMA
dead
[7]
Idle
release
Bus