H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 198

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.5.6
Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4
states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or
disabling of wait insertion, and do not affect the number of access states. When the corresponding
bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
The 4 states of the basic timing consist of one T
output cycle), and two T
Rev. 3.00 Sep 15, 2006 page 164 of 988
REJ09B0330-0300
Note: n = 2 to 5
Read
Write
Basic Timing
(UWE, LWE)
(UWE, LWE)
CAS, LCAS
HWR, LWR
HWR, LWR
CSn (RAS)
D
D
A
15
15
23
to D
to D
to A
Figure 6.15 Basic Access Timing (2-WE System)
c
0
0
0
(column address output cycle) states, T
T
p
p
(precharge cycle) state, one T
row
T
r
T
c1
c1
and T
column
c2
.
T
r
(row address
c2