H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 224

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.10.4
Figure 6.37 shows the timing for transition to the bus-released state.
6.10.5
When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external
bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the
external bus release function is to be used in sleep mode.
Rev. 3.00 Sep 15, 2006 page 190 of 988
REJ09B0330-0300
Address bus
HWR, LWR
Data bus
Transition Timing
Usage Note
[1]
[2]
[3]
[4]
[5]
BREQ
BACK
RD
AS
Low level of BREQ pin is sampled at rise of T
BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master.
BREQ pin state is still sampled in external bus released state.
High level of BREQ pin is sampled.
BACK pin is driven high, ending bus release cycle.
Figure 6.37 Bus-Released State Transition Timing
T
0
CPU cycle
T
Address
1
[1]
Minimum
1 state
T
2
[2]
2
External bus released state
state.
[3]
High impedance
High impedance
High impedance
High impedance
High impedance
[4]
[5]
cycle
CPU