H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 204

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
(1) Burst Access (Fast Page Mode) Operation Timing
Figure 6.20 shows the operation timing for burst access. When there are consecutive access cycles
for DRAM space, the CAS signal and column address output cycles (two states) continue as long
as the row address is the same for consecutive access cycles. The row address used for the
comparison is set with bits MXC1 and MXC0 in MCR.
The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion
method and timing are the same as for full access. For details, see section 6.5.8, Wait Control.
Rev. 3.00 Sep 15, 2006 page 170 of 988
REJ09B0330-0300
Read
Write
Note: n = 2 to 5
CAS, LCAS
Figure 6.20 Operation Timing in Fast Page Mode (2-WE System)
CSn (RAS)
HWR (WE)
HWR ( WE)
D
D
A
15
15
23
to D
to D
to A
0
0
0
T
p
row
T
r
T
c1
column1
T
c2
T
c1
column2
T
c2