H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 170

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.2.6
MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number
of precharge cycles, access mode, address multiplexing shift size, and the number of wait states
inserted during refreshing, when areas 2 to 5 are designated as DRAM interface.
MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized
by a manual reset or in software standby mode.
Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (T
used when areas 2 to 5 designated as DRAM space are accessed.
Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5
designated as DRAM space. DRAM space burst access is performed in fast page mode.
Bit 5—RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access
to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the
RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode).
RAS down mode cannot be used with the 2-CAS method. When selecting RAS down mode, set
the BE bit to 1.
Rev. 3.00 Sep 15, 2006 page 136 of 988
REJ09B0330-0300
Bit 7
TPC
0
1
Bit 6
BE
0
1
Bit
Initial value
R/W
Memory Control Register (MCR)
Description
1-state precharge cycle is inserted
2-state precharge cycle is inserted
Description
Burst disabled (always full access)
For DRAM space access, access in fast page mode
:
:
:
TPC
R/W
7
0
R/W
BE
6
0
RCDM
R/W
5
0
CW2
R/W
4
0
MXC1
R/W
3
0
MXC0
R/W
2
0
RLW1
R/W
1
0
(Initial value)
(Initial value)
RLW0
R/W
P
0
0
) is to be