H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 810

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
Appendix A Instruction Set
A.4
The tables in this section can be used to calculate the number of states required for instruction
execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and
other cycles occurring in each instruction. Table A.4 indicates the number of states required for
each cycle. The number of states required for execution of an instruction can be calculated from
these two tables as follows:
Examples: Advanced mode, program code and stack located in external memory, on-chip
supporting modules accessed in two states with 8-bit bus width, external devices accessed in three
states with one wait state and 16-bit bus width.
1. BSET #0, @FFFFC7:8
2. JSR @@30
Rev. 3.00 Sep 15, 2006 page 776 of 988
REJ09B0330-0300
From table A.5:
I = L = 2, J = K = M = N = 0
From table A.4:
S
Number of states required for execution = 2
From table A.5:
I = J = K = 2, L = M = N = 0
From table A.4:
S
Number of states required for execution = 2
Execution states = I
I
I
= 4, S
= S
J
Number of States Required for Instruction Execution
= S
L
K
= 2
= 4
S
I
+ J
S
J
+ K
S
K
+ L
4 + 2
4 + 2
S
L
+ M
2 = 12
4 + 2
S
M
4 = 24
+ N
S
N

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