H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 132

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.2.5
ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 0—IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to
IRQ0 interrupt requests.
Note: n = 7 to 0
Rev. 3.00 Sep 15, 2006 page 98 of 988
REJ09B0330-0300
Bit n
IRQnF
0
1
Bit
Initial value
R/W
Note: * Only 0 can be written, to clear the flag.
IRQ Status Register (ISR)
Description
[Clearing conditions] (Initial value)
[Setting conditions]
:
:
:
Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
When IRQn interrupt exception handling is executed when falling, rising, or both-
edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA
= 0)
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
R/(W) *
IRQ7F
7
0
R/(W) *
IRQ6F
6
0
R/(W) *
IRQ5F
5
0
R/(W) *
IRQ4F
4
0
R/(W) *
IRQ3F
3
0
R/(W) *
IRQ2F
2
0
R/(W) *
IRQ1F
1
0
R/(W) *
IRQ0F
0
0