H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 589

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

13.2.6
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
SCR is initialized to H'00 by a reset, and in standby mode or module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Note:
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI)
request and receive error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Note:
Bit 7
TIE
0
1
Bit 6
RIE
0
1
Bit
Initial value
R/W
* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
* RXI and ERI interrupt request cancellation can be performed by reading 1 from the
Serial Control Register (SCR)
then clearing it to 0, or clearing the TIE bit to 0.
RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the
RIE bit to 0.
Description
Transmit data empty interrupt (TXI) requests disabled *
Transmit data empty interrupt (TXI) requests enabled
Description
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
disabled *
Receive data full interrupt (RXI) request and receive error interrupt (ERI) request
enabled
:
:
:
R/W
TIE
7
0
R/W
RIE
6
0
R/W
TE
5
0
Section 13 Serial Communication Interface (SCI)
R/W
RE
4
0
Rev. 3.00 Sep 15, 2006 page 555 of 988
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
REJ09B0330-0300
R/W
1
0
(Initial value)
(Initial value)
CKE0
R/W
0
0