H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 260

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an
interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when
DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer
break interrupt request to the CPU or DTC.
A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt
handling routine, or by performing processing to continue transfer by setting the DTME bit to 1.
Bit 3—Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1
transfer break interrupt.
Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0
transfer break interrupt.
Rev. 3.00 Sep 15, 2006 page 226 of 988
REJ09B0330-0300
Bit 3
DTIE1B
0
1
Bit 1
DTIE0B
0
1
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
Description
Transfer break interrupt disabled
Transfer break interrupt enabled
(Initial value)
(Initial value)