H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 182

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
6.4
6.4.1
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table
6.3).
6.4.2
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D
for the area being accessed (8-bit access space or 16-bit access space) and the data size.
8-Bit Access Space
Figure 6.4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D
accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and
a longword transfer instruction, as four byte accesses.
Rev. 3.00 Sep 15, 2006 page 148 of 988
REJ09B0330-0300
Byte size
Word size
Longword size
Basic Bus Interface
Overview
Data Size and Data Alignment
Figure 6.4 Access Sizes and Data Alignment Control (8-Bit Access Space)
15
to D
15
to D
8
) or lower data bus (D
8
) is always used for accesses. The amount of data that can be
1st bus cycle
2nd bus cycle
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
7
D
to D
15
Upper data bus
0
) is used according to the bus specifications
D
8
D
7
Lower data bus
D
0