H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 879

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H8S-2350

Manufacturer Part Number
H8S-2350
Description
16-Bit Single-Chip Microcomputer
Manufacturer
RENESAS [Renesas Technology Corp]
Datasheet
BCRH—Bus Control Register H
Bit
Initial value
Read/Write
:
:
:
Idle Cycle Insert 1
0
1
ICIS1
R/W
7
1
Idle cycle not inserted in case of successive external read cycles in different areas
Idle cycle inserted in case of successive external read cycles in different areas
Idle Cycle Insert 0
0
1
ICIS0
R/W
Idle cycle not inserted in case of successive external read and external write cycles
Idle cycle inserted in case of successive external read and external write cycles
6
1
Area 0 Burst ROM Enable
0
1
BRSTRM
R/W
Area 0 is basic bus interface
Area 0 is burst ROM interface
5
0
Burst Cycle Select 1
0
1
BRSTS1
R/W
Burst cycle comprises 1 state
Burst cycle comprises 2 states
4
1
Burst Cycle Select 0
0
1
BRSTS0
H'FED4
R/W
Max. 4 words in burst access
Max. 8 words in burst access
Rev. 3.00 Sep 15, 2006 page 845 of 988
3
0
Note: When areas selected in DRAM space
RMTS2
RAM Type Select
0
1
RMTS2
R/W
RMTS1
are all 8-bit space, the PF
used as an I/O port, BREQO, or WAIT.
Appendix B Internal I/O Register
2
0
0
1
RMTS0
0
1
0
1
RMTS1
R/W
Area 5 Area 4 Area 3 Area 2
1
0
Normal
Normal space
space
REJ09B0330-0300
Normal space
DRAM space
Bus Controller
RMTS0
R/W
0
0
DRAM space
2
pin can be
DRAM
space

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