H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 153

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 5 Interrupt Controller
5.6.3
Operation
The interrupt controller has three main functions in DTC and DMAC control.
(1) Selection of Interrupt Source
With the DMAC, the activation source is input directly to each channel. The activation source for
each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected
activation source is to be managed by the DMAC can be selected with the DTA bit of DMABCR.
When the DTA bit is set to 1, the interrupt source constituting that DMAC activation source is not
a DTC activation source or CPU interrupt source.
For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC
activation request or CPU interrupt request with the DTCE bit of DTCEA to DTCEF in the DTC.
After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the
CPU in accordance with the specification of the DISEL bit of MRB in the DTC.
When the DTC has performed the specified number of data transfers and the transfer counter value
is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data
transfer.
(2) Determination of Priority
The DTC activation source is selected in accordance with the default priority order, and is not
affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector
Table, for the respective priorities.
With the DMAC, the activation source is input directly to each channel.
(3) Operation Order
If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC
data transfer is performed first, followed by CPU interrupt exception handling.
If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU
interrupt source, operations are performed for them independently according to their respective
operating statuses and bus mastership priorities.
Rev. 3.00 Sep 15, 2006 page 119 of 988
REJ09B0330-0300