H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 218

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
(4) Usage Notes
When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of
consecutive reads between different areas, for example, if the second access is a DRAM access,
only a T
However, in burst access in RAS down mode these settings are enabled, and an idle cycle is
inserted. The timing in this case is shown in figures 6.35 (a) and (b).
Rev. 3.00 Sep 15, 2006 page 184 of 988
REJ09B0330-0300
p
cycle is inserted, and a T
Address bus
Figure 6.34 Example of DRAM Access after External Read
Data bus
RD
T
I
1
cycle is not. The timing in this case is shown in figure 6.34.
External read
T
2
T
3
T
p
DRAM space read
T
r
T
c1
T
c2