H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 172

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 6 Bus Controller
Bits 1 and 0—Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the
number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This
setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled.
6.2.7
DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh
counter clock, and controls the refresh timer.
DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not
initialized by a manual reset or in software standby mode.
Bit 7—Refresh Control (RFSHE): Selects whether or not refresh control is performed. When
refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control
is not performed in normal mode.
Rev. 3.00 Sep 15, 2006 page 138 of 988
REJ09B0330-0300
Bit 1
RLW1
0
1
Bit 7
RFSHE
0
1
Bit
Initial value
R/W
DRAM Control Register (DRAMCR)
Bit 0
RLW0
0
1
0
1
Description
Refresh control is not performed
Refresh control is performed
:
:
:
RFSHE
R/W
7
0
Description
No wait state inserted
1 wait state inserted
2 wait states inserted
3 wait states inserted
RCW
R/W
6
0
RMODE
R/W
5
0
CMF
R/W
4
0
CMIE
R/W
3
0
CKS2
R/W
2
0
CKS1
R/W
1
0
(Initial value)
(Initial value)
CKS0
R/W
0
0