H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 276

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 7 DMA Controller (DMAC)
7.5.4
Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to
0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer
request, and this is executed the number of times specified in ETCR. On completion of the
specified number of transfers, MAR and ETCRL are automatically restored to their original
settings and operation continues.
One address is specified by MAR, and the other by IOAR. The transfer direction can be specified
by the DTDIR bit in DMACR.
Table 7.8 summarizes register functions in repeat mode.
Table 7.8
Legend:
MAR:
IOAR: I/O address register
ETCR: Transfer count register
DTDIR: Data transfer direction bit
Rev. 3.00 Sep 15, 2006 page 242 of 988
REJ09B0330-0300
Register
23
23
H'FF
Memory address register
Repeat Mode
15
Register Functions in Repeat Mode
MAR
IOAR
7
7
ETCRH
ETCRL
0
0
0
0
DTDIR = 0
Source
address
register
Destination
address
register
Holds number of
transfers
Transfer counter
Function
DTDIR = 1
Destination
address
register
Source
address
register
Initial Setting
Start address
of transfer
destination or
transfer source
Start address
of transfer
source or
transfer
destination
Number of
transfers
Number of
transfers
Operation
Incremented/
decremented every
transfer. Initial
setting is restored
when value reaches
H'0000
Fixed
Fixed
Decremented every
transfer. Loaded
with ETCRH value
when count reaches
H'00