H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 435

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Port F Data Register (PFDR)
PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF
PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior
state after a manual reset, and in software standby mode.
Port F Register (PORTF)
PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port
F pins (PF
If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F
read is performed while PFDDR bits are cleared to 0, the pin states are read.
After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin
states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and
in software standby mode.
Bit
Initial value
R/W
Bit
Initial value
R/W
Note: * Determined by state of pins PF
Pins PF
BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1
makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an
input port.
Modes 3 and 7 [H8S/2351 only]
Setting a PFDDR bit to 1 makes the corresponding port F pin PF
the case of pin PF
7
2
to PF
to PF
:
:
:
:
:
:
0
) must always be performed on PFDR.
0
PF7DR
are designated as bus control input/output pins (LCAS, WAIT, BREQO,
PF7
R/W
—*
R
7
7
7
0
, the output pin. Clearing the bit to 0 makes the pin an input port.
PF6DR
PF6
R/W
—*
R
6
6
0
PF5DR
PF5
R/W
—*
R
5
5
0
7
to PF
PF4DR
0
PF4
.
—*
R/W
R
4
4
0
Rev. 3.00 Sep 15, 2006 page 401 of 988
PF3DR
PF3
R/W
—*
R
3
3
0
6
PF2DR
to PF
PF2
—*
R/W
R
2
2
0
0
an output port, or in
PF1DR
Section 9 I/O Ports
PF1
REJ09B0330-0300
R/W
—*
R
1
1
0
7
PF0DR
PF0
to PF
—*
R/W
R
0
0
0
0
).