H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 434

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Section 9 I/O Ports
9.13.2
Table 9.23 shows the port F register configuration.
Table 9.23 Port F Registers
Notes: 1. Lower 16 bits of the address.
Port F Data Direction Register (PFDDR)
PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port F. PFDDR cannot be read; if it is, an undefined value will be read.
PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2,
and 4 to 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in
software standby mode. The OPE bit in SBYCR is used to select whether the bus control output
pins retain their output state or become high-impedance when a transition is made to software
standby mode.
Rev. 3.00 Sep 15, 2006 page 400 of 988
REJ09B0330-0300
Name
Port F data direction register
Port F data register
Port F register
Bit
Modes 1, 2, 4 to 6
Initial value
R/W
Modes 3 and 7
Initial value
R/W
Modes 1, 4, and 5 [H8S/2350]; modes 1, 2, and 4 to 6 [H8S/2351]
Pin PF
input port when the bit is cleared to 0.
The input/output direction specified by PFDDR is ignored for pins PF
automatically designated as bus control outputs (AS, RD, HWR, and LWR).
2. Initial value depends on the mode.
Register Configuration
7
functions as the output pin when the corresponding PFDDR bit is set to 1, and as an
:
:
:
:
:
PF7DDR
W
W
7
1
0
PF6DDR
W
W
6
0
0
Abbreviation
PFDDR
PFDR
PORTF
PF5DDR
W
W
5
0
0
PF4DDR
W
W
4
0
0
R/W
W
R/W
R
PF3DDR
W
W
3
0
0
Initial Value
H'80/H'00 *
H'00
Undefined
PF2DDR
W
W
2
0
0
6
to PF
2
PF1DDR
3
, which are
W
W
1
0
0
H'FF6E
H'FF5E
Address *
H'FEBE
PF0DDR
W
W
0
0
0
1