H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 265

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

7.4.2
DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC
transfer end pin output. A port can be set for output automatically, and a transfer end signal output,
by setting the appropriate bit.
DMATCR is initialized to H'00 by a reset, and in standby mode.
Bits 7 and 6—Reserved: Read-only bits, always read as 0.
Bit 5—Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output.
Bit 4—Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output.
The TEND pins are assigned only to channel B in short address mode.
The transfer end signal indicates the transfer cycle in which the transfer counter reached 0,
regardless of the transfer source. An exception is block transfer mode, in which the transfer end
signal indicates the transfer cycle in which the block counter reached 0.
Bits 3 to 0—Reserved: Read-only bits, always read as 0.
Bit 5
TEE1
0
1
Bit 4
TEE0
0
1
Bit
DMATCR
Initial value
R/W
DMA Terminal Control Register (DMATCR)
Description
TEND1 pin output disabled
TEND1 pin output enabled
Description
TEND0 pin output disabled
TEND0 pin output enabled
:
:
:
:
—
—
7
0
—
—
6
0
TEE1
R/W
5
0
TEE0
R/W
4
0
Rev. 3.00 Sep 15, 2006 page 231 of 988
—
—
3
0
Section 7 DMA Controller (DMAC)
—
—
2
0
REJ09B0330-0300
—
—
1
0
(Initial value)
(Initial value)
—
—
0
0