H8S-2350 RENESAS [Renesas Technology Corp], H8S-2350 Datasheet - Page 169

• Manufacturer Part Number: H8S-2350
• Description: 16-Bit Single-Chip Microcomputer
• Manufacturer: RENESAS [Renesas Technology Corp]

Bit 3—DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for
the DRAM interface.
Bit 2—Reserved: Only 1 should be written to this bit.
Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is
used for an external write cycle or DMAC single address cycle.
Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT
pin.
Bit 3
DDS
0
1
Bit 1
WDBE
0
1
Bit 0
WAITE
0
1
Description
When DMAC single address transfer is performed in DRAM space, full access is
always executed
DACK signal goes low from T
Burst access is possible when DMAC single address transfer is performed in DRAM
space
DACK signal goes low from T
Description
Write data buffer function not used
Write data buffer function used
Description
Wait input by WAIT pin disabled. WAIT pin can be used as I/O port.
Wait input by WAIT pin enabled
r
c1
or T
or T
1
2
cycle
cycle
Rev. 3.00 Sep 15, 2006 page 135 of 988
Section 6 Bus Controller
REJ09B0330-0300
(Initial value)
(Initial value)
(Initial value)