R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1018

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 19 Controller Area Network (RCAN-TL1)
Bits 15 to 0 — Timer Compare Match Register (TCMR2): Indicates the value of CYCTR
when compare match occurs.
(10) Tx-Trigger Time Selection Register (TTTSEL)
This register is a 16-bit read/write register and specifies the Tx-Trigger Time waiting for compare
match with Cycle Time. Only one bit is allowed to be set. Please don't set more bits than one, or
clear all bits.
This register may only be modified during configuration mode. The modification algorithm is
shown in figure 19.13.
Please note that this register is only indented for test and diagnosis. When not in test mode, this
register must not be written to and the returned value is not guaranteed.
• TTTSEL (Address = H'0A4)
Note: Only one bit is allowed to be set.
Bit 15: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Bits 14 to 8 — Specifies the Tx-Trigger Time waiting for compare match with CYCTR The bit 14
to 8 corresponds to Mailbox-30 to 24, respectively.
Bits 7 to 0: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Rev. 3.00 Sep. 28, 2009 Page 986 of 1650
REJ09B0313-0300
Initial value:
R/W:
Bit:
15
R
0
-
R/W
14
1
R/W
13
0
R/W
12
0
TTTSEL[14:8]
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R
7
0
-
R
6
0
-
R
5
0
-
R
4
0
-
R
3
0
-
R
2
0
-
R
1
0
-
R
0
0
-