R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 955

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Table 19.1 Roles of Mailboxes
(ET) shows that it works during merged arbitrating window, after completion of time-triggered
transmission.
MB31
MB30
MB29 - 24
MB23 - 16
MB15 - 1
MB0
MB15 to 1 (MB with timestamp)
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'100 + N*32
H'102 + N*32
H'104 + N*32
H'106 + N*32
H'108 + N*32
H'100 + N*32
H'102 + N*32
H'104 + N*32
H'106 + N*32
H'108 + N*32
MB0 (reception MB with timestamp)
H'110 + N*32
H'112 + N*32
H'110 + N*32
H'112 + N*32
Address
Address
LAFM
LAFM
IDE_
IDE_
IDE
IDE
15
15
0
0
Tx
OK
OK
OK
OK
OK
⎯
RTR
RTR
Event Trigger
14
14
0
0
0
0
MSG_DATA_0 (first Rx/Tx Byte)
MSG_DATA_0 (first Rx/Tx Byte)
NMC
NMC
13
13
0
0
0
0
MBC[1] is fixed to "1"
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
TimeStamp[15:0] (CYCTR[15:0] or CCR[5:0]/CYCTR[15:6] at SOF)
ATX DART
TimeStamp[15:0] (CYCTR[15:0] or CCR[5:0]/CYCTR[15:6] at SOF)
Rx
OK
OK
OK
OK
OK
OK
12
12
0
11
11
0
Tx
⎯
time reference
transmission in time
master mode
OK
⎯ (ET)
⎯ (ET)
⎯
10
10
Figure 19.3 Mailbox-N Structure
MBC[2:0]
MBC[2:0]
9
9
EXTID_LAFM[15:0]
EXTID_LAFM[15:0]
EXTID[15:0]
EXTID[15:0]
Data Bus
Data Bus
8
8
STDID_LAFM[10:0]
STDID_LAFM[10:0]
STDID[10:0]
STDID[10:0]
7
0
7
0
Time Trigger
6
0
6
0
5
0
5
0
Rx
time reference
reception
reception in time
slave mode
OK
OK
OK
OK
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
Section 19 Controller Area Network (RCAN-TL1)
4
0
4
0
Byte: 8-bit access, Word: 16-bit access, LW (LongWord) : 32-bit access
3
3
Rev. 3.00 Sep. 28, 2009 Page 923 of 1650
DLC[3:0]
DLC[3:0]
2
2
EXTID[17:16]
EXTID[17:16]
LAFM[17:16]
LAFM[17:16]
1
1
EXTID_
EXTID_
TimeStamp
available
available
⎯
⎯
available
available
0
0
Byte/Word/LW
Byte/Word/LW
Byte/Word/LW
Byte/Word/LW
Access Size
Access Size
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Word/LW
Word/LW
Word/LW
Word/LW
Word
Word
Word
Word
Word
Word
Remark
REJ09B0313-0300
Tx-Trigger
Time
⎯
available
available
⎯
⎯
⎯
TimeStamp
TimeStamp
Field Name
Field Name
Control 1
Control 0
Control 1
Control 0
LAFM
LAFM
Data
Data