R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 905

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Table 17.5 Time for Monitoring SCL

Note: pcyc = Pφ × cyc

The bit field ICCR1.CKS[3:0] should not be H'7 or H'F at the same time as NF2CYC.PRS = 1.

In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI

slower than the other masters, pulse cycles with an unexpected length will infrequently be output

Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other

Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.

In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer

is full, a stop condition may not be issued.

Use either 1 or 2 below as a measure against the situations above.

1. In master receive mode, read ICDRR before the rising edge of the 8th clock.

2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units.

Note on the Setting of ICCR1.CKS[3:0]

Settings for Multi-Master Operation

Note on Master Receive Mode

Time for Monitoring SCL

Rev. 3.00 Sep. 28, 2009 Page 873 of 1650

Section 17 I

C Bus Interface 3 (IIC3)

REJ09B0313-0300