R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 852

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
Section 16 Synchronous Serial Communication Unit (SSU)
(4)
Data Transmission/Reception
Figure 16.9 shows a flowchart example of simultaneous transmission/reception. The data
transmission/reception is performed combining the data transmission and data reception as
mentioned above. The data transmission/reception is started by writing transmit data to SSTDR
with TE = RE = 1. When the RDRF bit is set to 1, at the 8th rising edge of the transfer clock the
ORER bit in SSSR is set to 1, an overrun error (SSERI) is generated, and both transmission and
reception are stopped. Transmission and reception are not possible while the ORER bit is set to 1.
To resume transmission and reception, clear the ORER bit to 0.
Before switching transmission mode (TE = 1) or reception mode (RE = 1) to
transmission/reception mode (TE = RE = 1), clear the TE and RE bits to 0. When starting the
transfer, confirm that the TEND, RDRF, and ORER bits are cleared to 0 before setting the TE or
RE bit to 1.
Rev. 3.00 Sep. 28, 2009 Page 820 of 1650
REJ09B0313-0300

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