R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 19

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

11.8 MTU2 Output Pin Initialization ......................................................................................... 630
Section 12 Compare Match Timer (CMT).........................................................663
12.1 Features ............................................................................................................................ 663
12.2 Register Descriptions ......................................................................................................... 664
12.3 Operation ........................................................................................................................... 669
12.4 Interrupts............................................................................................................................ 670
12.5 Usage Notes ....................................................................................................................... 672
Section 13 Watchdog Timer (WDT)..................................................................675
13.1 Features ............................................................................................................................ 675
13.2 Input/Output Pin................................................................................................................. 677
13.3 Register Descriptions ......................................................................................................... 678
11.7.19 Cautions on Transition from Normal Operation or PWM Mode 1 to
11.7.20 Output Level in Complementary PWM Mode and Reset-Synchronized
11.7.21 Interrupts in Module Standby Mode ................................................................... 629
11.7.22 Simultaneous Capture of TCNT_1 and TCNT_2 in Cascade Connection.......... 629
11.8.1
11.8.2
11.8.3
11.8.4
12.2.1
12.2.2
12.2.3
12.2.4
12.3.1
12.3.2
12.4.1
12.4.2
12.4.3
12.5.1
12.5.2
12.5.3
12.5.4
13.3.1
13.3.2
13.3.3
Reset-Synchronized PWM Mode........................................................................ 628
PWM Mode......................................................................................................... 629
Operating Modes................................................................................................. 630
Reset Start Operation .......................................................................................... 630
Operation in Case of Re-Setting Due to Error During Operation, etc................. 631
Overview of Initialization Procedures and Mode Transitions
in Case of Error during Operation, etc................................................................ 632
Compare Match Timer Start Register (CMSTR) ................................................ 665
Compare Match Timer Control/Status Register (CMCSR) ................................ 666
Compare Match Counter (CMCNT) ................................................................... 668
Compare Match Constant Register (CMCOR) ................................................... 668
Interval Count Operation .................................................................................... 669
CMCNT Count Timing....................................................................................... 669
Interrupt Sources and DMA Transfer Requests .................................................. 670
Timing of Compare Match Flag Setting ............................................................. 670
Timing of Compare Match Flag Clearing........................................................... 671
Conflict between Write and Compare-Match Processes of CMCNT ................. 672
Conflict between Word-Write and Count-Up Processes of CMCNT ................. 673
Conflict between Byte-Write and Count-Up Processes of CMCNT................... 674
Compare Match between CMCNT and CMCOR ............................................... 674
Watchdog Timer Counter (WTCNT).................................................................. 678
Watchdog Timer Control/Status Register (WTCSR).......................................... 679
Watchdog Reset Control/Status Register (WRCSR) .......................................... 681
Rev. 3.00 Sep. 28, 2009 Page xvii of xxx
REJ09B0313-0300