R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 223

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

6.8.3
If an interrupt occurs and usage of the register banks is enabled for the interrupt accepted by the
CPU in a state where saving has been performed to all register banks, automatic saving to the
stack is performed instead of register bank saving if the BOVE bit in the bank number register
(IBNR) is cleared to 0. If the BOVE bit in IBNR is set to 1, register bank overflow exception
occurs and data is not saved to the stack.
Save and restore operations when using the stack are as follows:
(1)
1. The status register (SR) and program counter (PC) are saved to the stack during interrupt
2. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are saved to
3. The register bank overflow bit (BO) in SR is set to 1.
4. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
(2)
When the RESBANK (restore from register bank) instruction is executed with the register bank
overflow bit (BO) in SR set to 1, the CPU operates as follows:
1. The contents of the banked registers (R0 to R14, GBR, MACH, MACL, and PR) are restored
2. The bank number bit (BN) value in the bank number register (IBNR) remains set to the
exception handling.
the stack. The registers are saved to the stack in the order of MACL, MACH, GBR, PR, R14,
R13, …, R1, and R0.
maximum value of 15.
from the stack. The registers are restored from the stack in the order of R0, R1, …, R13, R14,
PR, GBR, MACH, and MACL.
maximum value of 15.
Saving to Stack
Restoration from Stack
Save and Restore Operations after Saving to All Banks
Rev. 3.00 Sep. 28, 2009 Page 191 of 1650
Section 6 Interrupt Controller (INTC)
REJ09B0313-0300