R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1644

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Appendix
Rev. 3.00 Sep. 28, 2009 Page 1612 of 1650
REJ09B0313-0300
2. After the chip has shifted to the power-on reset state from deep standby mode by the
3. The week keeper circuits included in the I/O pins are turned off.
4. When pins for the connection with a crystal resonator are not used, the input pins
5. The initial pin function depends on the data bus width of area 0 (see section 25, Pin
6. Depends on the setting of the CKOEN bit in the frequency control register (FRQCR) of
7. Depends on the setting of the HIZ bit in the standby control register 3 (STBCR3) (see
8. Depends on the setting of the HIZMEM bit in the common control register (CMNCR) of
9. Depends on the setting of the HIZCNT bit in the common control register (CMNCR) of
10. Depends on the setting of the corresponding bit in the deep standby cancel source
11. Depends on the setting of the RTCEN bit in the RTC control register 2 (RCR2) of the
12. Depends on the AXTALE bit in the standby control register (STBCR) (see section 28,
13. When the CS0KEEPE bit in the deep standby control register 2 (DSCTR2) is 1, this pin
14. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
15. These are the pin states in product chip mode (ASEMD = H). See the Emulation
input on any of pins NMI, MRES, and IRQ7 to IRQ0, the pins retain the state until the
IOKEEP bit in the deep standby cancel source flag register (DSFR) is cleared (see
section 28, Power-Down Modes).
(EXTAL, RTC_X1, AUDIO_X1, and USB_X1) must be fixed (pulled up, pulled down,
connected to power supply, or connected to ground) and the output pins (XTAL,
RTC_X2, AUDIO_X2, and USB_X2) must be open.
Function Controller (PFC)).
the CPG (see section 4, Clock Pulse Generator (CPG)).
section 28, Power-Down Modes).
the BSC (see section 9, Bus State Controller (BSC)).
the BSC (see section 9, Bus State Controller (BSC)).
select register (DSSSR) (see section 28, Power-Down Modes).
RTC (see section 14, Realtime Clock (RTC)).
Power-Down Modes).
retains the state of deep standby mode. When the CS0KEEPE bit is 0, this pin enters
the state of a power-on reset (see section 28, Power-Down Modes).
Manual for the pin states in ASE mode (ASEMD = L).