R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 526

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.8
TADCR is a 16-bit readable/writable register that enables or disables A/D converter start requests
and specifies whether to link A/D converter start requests with interrupt skipping operation. The
MTU2 has one TADCR in channel 4.
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 494 of 1650
REJ09B0313-0300
Bit
0
Bit
15, 14
13 to 8 —
7
Note:
R/W:
Bit:
*
Do not set to 1 when complementary PWM mode is not selected.
Bit Name
I1AE
Bit Name
BF[1:0]
UT4AE
R/W
Timer A/D Converter Start Request Control Register (TADCR)
15
0
BF[1:0]
R/W
14
0
13
R
0
-
Initial
Value
0
Initial
Value
00
All 0
0
12
R
0
-
11
R
0
-
R/W
R/W
R/W
R/W
R
R/W
10
R
0
-
Description
Input Capture Enable
Specifies whether to include the TIOC1A pin in the
TGRA_2 input capture conditions.
0: Does not include the TIOC1A pin in the TGRA_2
1: Includes the TIOC1A pin in the TGRA_2 input
Description
TADCOBRA_4/TADCOBRB_4 Transfer Timing Select
Select the timing for transferring data from
TADCOBRA_4 and TADCOBRB_4 to TADCORA_4
and TADCORB_4.
For details, see table 11.27.
Reserved
These bits are always read as 0. The write value should
always be 0.
Up-Count TRG4AN Enable
Enables or disables A/D converter start requests
(TRG4AN) during TCNT_4 up-count operation.
0: A/D converter start requests (TRG4AN) disabled
1: A/D converter start requests (TRG4AN) enabled
R
9
0
-
input capture conditions
capture conditions
during TCNT_4 up-count operation
during TCNT_4 up-count operation
R
8
0
-
UT4AE DT4AE UT4BE DT4BE ITA3AE ITA4VE ITB3AE ITB4VE
R/W
7
0
R/W
0*
6
R/W
5
0
R/W
0*
4
R/W
0*
3
R/W
0*
2
R/W
0*
1
R/W
0*
0