R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1660

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Rev. 3.00 Sep. 28, 2009 Page 1628 of 1650
REJ09B0313-0300
Item
18.3 Register
Description
Table 18.2 Register
Description
18.3.1 Control Register
(SSICR)
18.5.1 Limitations from
Underflow or Overflow
during DMA Operation
19.7 CAN Bus Interface 1015
Page
879
885
912
Revision (See Manual for Details)
Table amended
Channel
Table amended
Title amended and description replaced
Description amended
A bus transceiver IC is necessary to connect this LSI to a
CAN bus. A Renesas HA13721 transceiver IC and its
compatible products are recommended. As the CRx and CTx
pins use 3 V, an external level shifter is necessary. Figure
19.27 shows a sample connection diagram.
Bit
0
1
2
3
3
Bit Name
MUEN
Register Name
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
Control register 2
Status register 2
Transmit data register 2
Receive data register 2
Control register 3
Status register 3
Transmit data register 3
Receive data register 3
Initial
Value
0
R/W
R/W
Abbrevia-
tion
SSICR_0
SSISR_0
SSITDR_0
SSIRDR_0
SSICR_1
SSISR_1
SSITDR_1
SSIRDR_1
SSICR_2
SSISR_2
SSITDR_2
SSIRDR_2
SSICR_3
SSISR_3
SSITDR_3
SSIRDR_3
Description
Mute Enable
0: Module is not muted.
1: Module is muted.
Note: When mute is enabled, the serial data to be output
is replaced with zeros, but data transfer within the
module does not stop. Therefore, dummy data
must be written to SSITRD to prevent a transmit
underflow from occurring.
R/W
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
Initial Value
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
Address
H'FFFFC000
H'FFFFC004
H'FFFFC008
H'FFFFC00C
H'FFFFC800
H'FFFFC804
H'FFFFC808
H'FFFFC80C
H'FFFFD000
H'FFFFD004
H'FFFFD008
H'FFFFD00C
H'FFFFD800
H'FFFFD804
H'FFFFD808
H'FFFFD80C
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32