R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 677

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

(13) Operation when Error Occurs during PWM Mode 2 Operation, and Operation is
Figure 11.125 shows an explanatory diagram of the case where an error occurs in PWM mode 2
and operation is restarted in normal mode after re-setting.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Set normal mode.
11. Initialize the pins with TIOR.
12. Set MTU2 output with the PFC.
13. Operation is restarted by TSTR.
MTU2 module output
After a reset, MTU2 output is low and ports are in the high-impedance state.
Set PWM mode 2.
compare-match occurrence. In PWM mode 2, the cycle register pins are not initialized. In the
example, TIOC *A is the cycle register.)
Set MTU2 output with the PFC.
The count operation is started by TSTR.
Output goes low on compare-match occurrence.
An error occurs.
Set port output with the PFC and output the inverse of the active level.
The count operation is stopped by TSTR.
Initialize the pins with TIOR. (The example shows initial high output, with low output on
Restarted in Normal Mode
n = 0 to 15
Figure 11.125 Error Occurrence in PWM Mode 2, Recovery in Normal Mode
Port output
TIOC*A
TIOC*B
PEn
PEn
RESET
1
(PWM2)
TMDR
2
Hi-Z
Hi-Z
(1 init
0 out)
TIOR
3
Not initialized (cycle register)
(MTU2)
PFC
4
TSTR
(1)
5
Match
6
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
occurs
Error
7
(PORT)
PFC
Rev. 3.00 Sep. 28, 2009 Page 645 of 1650
8
TSTR
(0)
9
(normal)
TMDR
10
0 out)
TIOR
(1 init
11
(MTU2)
REJ09B0313-0300
PFC
12
TSTR
13
(1)