R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 251

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

• Structure: Instructions/data separated, 4-way set associative

• Way lock function (operand cache only): Way 2 and way 3 are lockable

• Line size: 16 bytes

• Number of entries: 128 entries/way

• Write system: Write-back/write-through selectable

• Replacement method: Least-recently-used (LRU) algorithm

The cache separates data and instructions and uses a 4-way set associative system. It is composed

of four ways (banks), each of which is divided into an address section and a data section.

Each of the address and data sections is divided into 128 entries per way. The data section of the

entry is called a line. Each line consists of 16 bytes (4 bytes × 4). The data capacity per way is 2

Kbytes (16 bytes × 128 entries), with a total of 8 Kbytes in the cache as a whole (4 ways). Figure

8.1 shows the operand cache structure. The instruction cache structure is the same as the operand

cache structure except for not having the U bit.

Instruction cache: 8 Kbytes

Operand cache: 8 Kbytes

Cache Structure

Section 8 Cache

Rev. 3.00 Sep. 28, 2009 Page 219 of 1650

REJ09B0313-0300

Section 8 Cache