R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 269

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

Specific cache entries can be invalidated by writing 0 to the entry's V bit in the memory mapping

cache access. When the A bit is 1, the tag address specified by the write data is compared to the

tag address within the cache selected by the entry address, and data is written to the bits V and U

specified by the write data when a match is found. If no match is found, there is no operation.

When the V bit of an entry in the address array is set to 0, the entry is written back if the entry's U

An example when a write data is specified in R0 and an address is specified in R1 is shown below.

The data section of a specific cache entry can be read by the memory mapping cache access. The

longword indicated in the data field of the data array in figure 8.4 is read into the register.

An example when an address is specified in R0 and data is read in R1 is shown below.

; R0=H'0110 0010; tag address(28-11)=B'0 0001 0001 0000 0000 0, U=0, V=0

; R1=H'F080 0088; operand cache address array access, entry=B'000 1000, A=1

; R0=H'F100 004C; instruction cache data array access, entry=B'000 0100,

; Way=0, longword address=3

MOV.L R0,@R1

MOV.L @R0,R1

Invalidating Specific Entries

Reading the Data of a Specific Entry

Usage Examples

Rev. 3.00 Sep. 28, 2009 Page 237 of 1650

REJ09B0313-0300

Section 8 Cache