R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1034

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 19 Controller Area Network (RCAN-TL1)
• Function to be implemented by software
Some of the TTCAN functions need to be implemented in software. The main details are reported
hereafter. Please refer to ISO-11898-4 for more details.
Rev. 3.00 Sep. 28, 2009 Page 1002 of 1650
REJ09B0313-0300
Cycle Time
= Time_Ref
Slave
<Configuration> Cycle Time varies between L and Time_Ref + L
<Normal Operation>
CCR = 0
⎯ Change from Init_Watch_Trigger to Watch_Trigger
⎯ Message status count
Cycle Time = 0
L
RCAN-TL1 offers the two registers TCMR0 and TCMR2 as H/W support for
Init_Watch_Trigger and Watch_Trigger respectively. The SW is requested to enable
TCMR0 and disable TCMR2 up to the first reference message is detected on the CAN Bus
and then disable TCMR0 and enable TCMR2.- Schedule Synchronization state machine.
Only reception of Next_is_Gap interrupt is supported. The application needs to take care of
stopping all transmission at the end of the current basic cycle by setting the related TXCR
flags.Master-Slave Mode control.
Only automatic cycle time synchronization and CCR increment is supported.
Software has to count scheduling errors for periodic messages in exclusive windows.
copy CCR from received time reference
CCR = 1
= Time_Ref + L
Ref_Mark and CCR are updated
at successful end of time reference reception
= L
Time_Mark 1
TTT in MB24
Time_Mark 1
TTT in MB24
Time_Mark 1
TTT in MB24
Time_Mark 2
TTT in MB25
Time_Mark 2
TTT in MB25
Time_Mark 2
TTT in MB25
Figure 19.20 Time Slave
Time_Mark 3
TTT in MB26
Time_Mark 3
TTT in MB26
Time_Mark 3
TTT in MB26
Time_Mark 4
TTT in MB27
Time_Mark 4
TTT in MB27
Time_Mark 4
TTT in MB27
Time_Mark 5
TTT in MB28
Time_Mark 5
TTT in MB28
Time_Mark 5
TTT in MB28
Time_Mark 6
TTT in MB29
Time_Mark 6
TTT in MB29
Time_Mark 6
TTT in MB29
= Time_Ref
Time_Ref
TTT in MB30
CCR isn't incremented unlike time master
Time_Ref
TTT in MB30
Time_Ref
TTT in MB30
capture timestamp
at SOF of reception
= Time_Ref + L
CCR = 0
Watch_Trigger
TCMR2