R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 820

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 15 Serial Communication Interface with FIFO (SCIF)
Synchronization
The receive margin in asynchronous mode can therefore be expressed as shown in equation 1.
Equation 1:
Where: M: Receive margin (%)
From equation 1, if F = 0, D = 0.5 and N = 16, the receive margin is 46.875%, as given by
equation 2.
Equation 2:
This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%.
Rev. 3.00 Sep. 28, 2009 Page 788 of 1650
REJ09B0313-0300
sampling timing
Data sampling
Receive data
Base clock
(RxD)
timing
M = (0.5 −
N: Ratio of clock frequency to bit rate (N = 16 or 8)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute deviation of clock frequency
When D = 0.5 and F = 0:
M = (0.5 − 1/(2 × 16)) × 100%
= 46.875%
Figure 15.19 Receive Data Sampling Timing in Asynchronous Mode
(Operation on a Base Clock with a Frequency 16 Times the Bit Rate)
0
1
2
8 clocks
Start bit
2N
3
1
4
) − (L − 0.5) F −
5
6
16 clocks
7
8
9 10 11 12 13 14 15
–7.5 clocks
D − 0.5
N
(1 + F) × 100 %
0
1
+7.5 clocks
2
3
4
D0
5
6
7
8
9
10 11 12 13 14 15
0
1
2
D1
3
4
5