R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 474

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 10 Direct Memory Access Controller (DMAC)
Figure 10.17 shows the TEND output timing.
The unit of the DMA transfer is divided into multiple bus cycles when 16-byte transfer is
performed for an 8-bit, 16-bit, or 32-bit external device, when longword access is performed for
an 8-bit or 16-bit external device, or when word access is performed for an 8-bit external device.
When a setting is made so that the DMA transfer size is divided into multiple bus cycles and the
CS signal is negated between bus cycles, note that DACK and TEND are divided like the CS
signal for data alignment as shown in figure 10.18. Figures 10.13 to 10.17 show the cases where
DACK and TEND are not divided in the DMA transfer.
Rev. 3.00 Sep. 28, 2009 Page 442 of 1650
REJ09B0313-0300
CKIO
Bus cycle
DREQ
DACK
TEND
Figure 10.17 Example of DMA Transfer End Signal Timing
DMAC
(Cycle Steal Mode Level Detection)
CPU
End of DMA transfer
DMAC
CPU
CPU