R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 516

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.4
The TIER registers are 8-bit readable/writable registers that control enabling or disabling of
interrupt requests for each channel. The MTU2 has six TIER registers, two for channel 0 and one
each for channels 1 to 4.
• TIER_0, TIER_1, TIER_2, TIER_3, TIER_4
Rev. 3.00 Sep. 28, 2009 Page 484 of 1650
REJ09B0313-0300
Bit
7
6
5
Bit Name
TTGE
TTGE2
TCIEU
Timer Interrupt Enable Register (TIER)
Initial value:
Initial
Value
0
0
0
R/W:
Bit:
TTGE TTGE2 TCIEU TCIEV TGIED TGIEC TGIEB TGIEA
R/W
7
0
R/W
R/W
R/W
R/W
R/W
6
0
Description
A/D Converter Start Request Enable
Enables or disables generation of A/D converter start
requests by TGRA input capture/compare match.
0: A/D converter start request generation disabled
1: A/D converter start request generation enabled
A/D Converter Start Request Enable 2
Enables or disables generation of A/D converter start
requests by TCNT_4 underflow (trough) in
complementary PWM mode.
In channels 0 to 3, bit 6 is reserved. It is always read as
0 and the write value should always be 0.
0: A/D converter start request generation by TCNT_4
1: A/D converter start request generation by TCNT_4
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channels 0, 3, and 4, bit 5 is reserved. It is always
read as 0 and the write value should always be 0.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
R/W
5
0
underflow (trough) disabled
underflow (trough) enabled
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0