R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 344

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
9.5.5
MPX-I/O Interface
Access timing for the MPX space is shown below. In the MPX space, CS5, AH, RD, and WEn
signals control the accessing. The basic access for the MPX space consists of 2 cycles of address
output followed by an access to a normal space. The bus width for the address output cycle or the
data input/output cycle is fixed to 8 bits or 16 bits. Alternatively, it can be 8 bits or 16 bits
depending on the address to be accessed.
Output of the addresses D15 to D0 or D7 to D0 is performed from cycle Ta2 to cycle Ta3.
Because cycle Ta1 has a high-impedance state, collisions of addresses and data can be avoided
without inserting idle cycles, even in continuous access cycles. Address output is increased to 3
cycles by setting the MPXW bit in CS5WCR to 1.
The RD/WR signal is output at the same time as the CS5 signal; it is high in the read cycle and
low in the write cycle.
The data cycle is the same as that in a normal space access.
Timing charts are shown in figures 9.11 to 9.13.
Rev. 3.00 Sep. 28, 2009 Page 312 of 1650
REJ09B0313-0300