R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 248

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 7 User Break Controller (UBC)
(3)
(Example 3-1)
• Register specifications
Rev. 3.00 Sep. 28, 2009 Page 216 of 1650
REJ09B0313-0300
BAR_0 = H'00314156, BAMR_0 = H'00000000, BBR_0 = H'0194, BAR_1= H'00055555,
BAMR_1 = H'00000000, BBR_1 = H'12A9, BDR_1 = H'78787878, BDMR_1 = H'0F0F0F0F,
BRCR = H'00000000
<Channel 0>
Address:
Bus cycle: Internal CPU bus/instruction fetch/read (operand size is not included in the
condition)
<Channel 1>
Address:
Data:
Bus cycle: Internal DMA bus/data access/write/byte
On channel 0, the setting of the internal CPU bus/instruction fetch is ignored.
On channel 1, a user break occurs when the DMAC writes byte data H'7x in address
H'00055555 on the internal DMA bus (access via the internal CPU bus does not generate a
user break).
Break Condition Specified for I Bus Data Access Cycle
H'00314156, Address mask: H'00000000
H'00055555, Address mask: H'00000000
H'00000078, Data mask: H'0000000F