R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1289

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

24.3.16 LCDC Interrupt Control Register (LDINTR)
LDINTR specifies where to control the Vsync interrupt of the LCD module. See also section
24.3.20, LCDC User Specified Interrupt Control Register (LDUINTR) and section 24.3.21, LCDC
User Specified Interrupt Line Number Register (LDUINTLNR) for interrupts. Note that
operations by this register setting and LCDC user specified interrupt control register (LDUINTR)
setting are independent.
Initial value:
Bit
15
14
13
R/W:
Bit:
MINT
R/W
EN
15
0
Bit Name
MINTEN
FINTEN
VSINTEN
FINT
R/W
EN
14
0
VSINT
R/W
13
EN
0
Initial
Value
0
0
0
VEINT
R/W
12
EN
0
MINTS FINTS VSINTS VEINTS
R/W
11
0
R/W
R/W
R/W
R/W
R/W
10
0
Memory Access Interrupt Enable
Description
Enables or disables an interrupt generation at the start
point of each vertical retrace line period for VRAM
access by LCDC.
0: Disables an interrupt generation at the start point of
1: Enables an interrupt generation at the start point of
Frame End Interrupt Enable
Enables or disables the generation of an interrupt after
the last pixel of a frame is output to LDC panel.
0: Disables an interrupt generation when the last pixel
1: Enables an interrupt generation when the last pixel of
Vsync Starting Point Interrupt Enable
Enables or disables the generation of an interrupt at the
start point of LCDC's Vsync.
0: Interrupt at the start point of the Vsyncl is disabled
1: Interrupt at the start point of the Vsync is enabled
R/W
9
0
each vertical retrace line period for VRAM access
each vertical retrace line period for VRAM access
of the frame is output
the frame is output
R/W
8
0
R
7
0
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Rev. 3.00 Sep. 28, 2009 Page 1257 of 1650
R
6
0
-
R
Section 24 LCD Controller (LCDC)
5
0
-
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R
1
0
-
R
0
0
-