R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 290

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 9 Bus State Controller (BSC)
Rev. 3.00 Sep. 28, 2009 Page 258 of 1650
REJ09B0313-0300
Bit
20
19
18 to 16
15 to 13
12, 11
Bit Name
BAS
⎯
WW[2:0]
⎯
SW[1:0]
Initial
Value
0
0
000
All 0
00
R/W
R/W
R
R/W
R
R/W
Description
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read/write timing and
1: Asserts the WEn signal during the read/write access
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Write Access Wait Cycles
Specify the number of cycles that are necessary for
write access.
000: The same cycles as WR[3:0] setting (number of
001: No cycle
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Delay Cycles from Address, CSn Assertion
to RD, WEn Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WEn assertion.
00: 0.5 cycles
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
asserts the RD/WR signal during the write access
cycle.
cycle and asserts the RD/WR signal at the write
timing.
read access wait cycles)