R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 8
R0K572030S000BE
Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Specifications of R0K572030S000BE
Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
- Current page: 8 of 1686
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• Description of Numbers and Symbols
Rev. 3.00 Sep. 28, 2009 Page vi of xxx
REJ09B0313-0300
Aspects of the notations for register names, bit names, numbers, and symbolic names in this
manual are explained below.
(1) Overall notation
(2) Register notation
(3) Number notation
(4) Notation for active-low
Note: The bit names and sentences in the above figure are examples and do not refer to
In descriptions involving the names of bits and bit fields within this manual, the modules and
registers to which the bits belong may be clarified by giving the names in the forms
"module name"."register name"."bit name" or "register name"."bit name".
The style "register name"_"instance number" is used in cases where there is more than one
instance of the same function or similar functions.
[Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0.
Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary),
hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn.
[Examples] Binary:
An overbar on the name indicates that a signal or pin is active-low.
[Example] WDTOVF
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
14.3 Operation
14.3.1 Interval Count Operation
specific data in this manual.
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter
input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in
CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in
CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000
and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time,
a f/4 clock is selected.
Hexadecimal: H'EFA0 or 0xEFA0
Decimal:
B'11 or 11
1234
(4)
(2)
Rev. 0.50, 10/04, page 416 of 914
(3)
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