R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1245

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

23.4.5
Data transfers of the data stage of control transfers are done using the default control pipe (DCP).
The DCP buffer memory is a 256-byte single buffer, and is a fixed area that is shared for both
control reading and control writing. The buffer memory can be accessed through the CFIFO port.
(1)
(a)
USQREQ, USBVAL, USBINDX, and USBLENG are the registers that are used to transmit a USB
request for setup transactions. Writing setup packet data to the registers and writing 1 to the
SUREQ bit in DCPCTR transmits the specified data for setup transactions. Upon completion of
transactions, the SUREQ bit is cleared to 0. The above USB request registers should not be
modified while SUREQ = 1. The device address for setup transactions is specified using the
DEVSEL bits in DCPMAXP.
When the data for setup transactions has been sent, a SIGN or SACK interrupt request is generated
according to the response received from the peripheral side (SIGN1 or SACK bits in INTSTS1),
by means of which the result of the setup transactions can be confirmed.
A data packet of DATA0 (USB request) is transmitted as the data packet for the setup transactions
regardless of the setting of the SQMON bit in DCPCTR.
(b)
Data transfers are done using the DCP buffer memory.
The access direction of the DCP buffer memory should be specified using the ISEL bit in
CFIFOSEL.
For the first data packet of the data stage, the data PID must be transferred as DATA1. Transaction
is done by setting the data PID = DATA1 and the PID bit = BUF using the SQSET bit in
DCPCFG. Completion of data transfer is detected using the BRDY and BEMP interrupts.
Setting continuous transfer mode allows data transfers over multiple packets. Note that when
continuous transfer mode is set for the receiving direction, the BRDY interrupt is not generated
until the buffer becomes full or a short packet is received (the integer multiple of the maximum
packet size, and less than 256 bytes).
For control write transfers, when the number of data bytes to be sent is the integer multiple of the
maximum packet size, software must control so as to send a zero-length packet at the end.
Control Transfers when the Host Controller Function is Selected
Setup Stage
Data Stage
Control Transfers (DCP)
Section 23 USB 2.0 Host/Function Module (USB)
Rev. 3.00 Sep. 28, 2009 Page 1213 of 1650
REJ09B0313-0300