R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1681

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

TCNT.................................................. 498
TCNTR ............................................... 983
TCNTS................................................ 513
TCR .................................................... 459
TDDR ................................................. 514
TDER.................................................. 520
TEC..................................................... 958
TESTMODE ..................................... 1111
TGCR.................................................. 511
TGR .................................................... 498
TICCR ................................................ 493
TIER ................................................... 484
TIOR................................................... 466
TITCNT .............................................. 517
TITCR................................................. 515
TMDR................................................. 463
TOCR1................................................ 504
TOCR2................................................ 507
TOER.................................................. 503
TOLBR ............................................... 510
TRWER .............................................. 502
TSR............................................. 487, 980
TSTR .................................................. 499
TSYR .................................................. 500
TTCR0 ................................................ 974
TTTSEL.............................................. 986
TWCR................................................. 521
TXACK0 ............................................ 966
TXACK1 ............................................ 965
TXCR0................................................ 965
TXCR1................................................ 964
TXPR0 ................................................ 963
TXPR1 ................................................ 962
UFRMNUM...................................... 1148
UMSR0 ............................................... 973
UMSR1 ............................................... 972
USBACSWR .................................... 1169
USBADDR ....................................... 1149
USBINDX ........................................ 1151
USBLENG........................................ 1152
Registers that should not be set in the
USB communication enabled state ....... 1194
Relationship between access size and
number of bursts ..................................... 332
Relationship between refresh requests and
bus cycles................................................ 351
Reset sequence ........................................ 990
Reset state ................................................. 91
Reset-synchronized PWM mode............. 552
Restoration from bank............................. 190
Restoration from stack ............................ 191
Restriction on DMAC usage ................... 787
Resume interrupt................................... 1189
RISC-type instruction set .......................... 54
Roles of mailboxes.................................. 923
Round to nearest ..................................... 102
Rounding................................................. 102
Round-robin mode .................................. 428
S
SACK interrupt ..................................... 1189
Saving to bank......................................... 189
Saving to stack ........................................ 191
Scan mode............................................. 1033
SCIF interrupt sources ............................ 785
SCIF timing........................................... 1578
SDRAM interface ................................... 316
Searching cache ...................................... 228
Sector access mode ............................... 1090
Self-refreshing......................................... 349
Sending a break signal ............................ 787
Serial bit clock control ............................ 911
Serial communication interface with
FIFO (SCIF)............................................ 721
Serial Sound Interface (SSI) ................... 875
USBREQ........................................... 1150
USBVAL........................................... 1151
WRCSR .............................................. 681
WTCNT .............................................. 678
WTCSR............................................... 679
Rev. 3.00 Sep. 28, 2009 Page 1649 of 1650
REJ09B0313-0300