R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1199

KIT DEV FOR SH7203

R0K572030S000BE

Manufacturer Part Number
R0K572030S000BE
Description
KIT DEV FOR SH7203
Manufacturer
Renesas Electronics America
Series
Renesas Starter Kits (RSK)r
Type
MCUr
Datasheets

Specifications of R0K572030S000BE

Contents
CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
Silicon Manufacturer
Renesas
Kit Contents
Board
Silicon Family Name
SH7203
Silicon Core Number
R5S72030W200FP
Tool / Board Applications
General Purpose MCU, MPU, DSP, DSC
Mcu Supported Families
SH7203
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
SH7203
Lead Free Status / Rohs Status
Compliant
23.3.36 PIPEn Control Registers (PIPEnCTR) (n = 1 to 7)
PIPEnCTR is a register that is used to confirm the buffer memory status for the corresponding
pipe, change and confirm the data PID sequence bit, determine whether the auto response mode is
set, determine whether the auto buffer clear mode is set, and set a response PID. This register can
be set regardless of the pipe selection in PIPESEL.
This register is initialized by a power-on reset or a software reset. PID[1:0] are initialized by a
USB bus reset.
Initial value:
Bit
15
14
13 to 11 ⎯
10
R/W:
Bit:
BSTS INBUFM
Bit Name
BSTS
INBUFM
ATREPM
15
R
0
14
R
0
13
R
0
-
12
Initial
Value
0
0
All 0
0
R
0
-
11
R
0
-
R/W
R
R
R
R/W
REPM ACLRM SQCLR SQSET SQMON
R/W
10
AT
0
R/W R/W*
9
0
Description
Buffer Status
0: Buffer access is disabled
1: Buffer access is enabled
The direction of buffer access, writing or reading,
depends on setting of the DIR bit in PIPECFG. For
details, see section 23.4, Operation.
IN Buffer Monitor
This bit is valid when the corresponding pipe is set to
the transmitting direction.
0: There is no data to be transmitted in the buffer
1: There is data to be transmitted in the buffer
Note: This bit is valid for PIPE1 to PIPE5.
Reserved
These bits are always read as 0. The write value
should always be 0.
Auto Response Mode
0: Normal mode
1: Auto response mode
Note: This bit is valid for PIPE1 to PIPE5.
memory
memory
8
0
1
Section 23 USB 2.0 Host/Function Module (USB)
R/W*
7
0
1
Rev. 3.00 Sep. 28, 2009 Page 1167 of 1650
R
6
0
R
5
0
-
R
4
0
-
R
3
0
-
REJ09B0313-0300
R
2
0
-
R/W
1
0
PID[1:0]
R/W
0
0

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