R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 847

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

User operation
User operation
User operation
(1) When 8-bit data length is selected (SSTDR0 is valid) with CPOS = 0 and CPHS = 0
(2) When 16-bit data length is selected (SSTDR0 and SSTDR1 are valid) with CPOS = 0 and CPHS = 0
(3) When 32-bit data length is selected (SSTDR0 to SSTDR3 are valid) with CPOS = 0 and CPHS = 0
LSI operation
LSI operation
LSI operation
(MSB first)
(MSB first)
(LSB first)
(LSB first)
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SSCK
TDRE
TEND
SSO
SSO
SSO
SSO
SSO
SCS
SCS
SCS
Figure 16.5 Example of Transmission Operation (SSU Mode)
Data written to SSTDR0 to SSTDR3
Data written to SSTDR0
Data written to SSTDR0 and SSTDR1
SSTXI interrupt
generated
Bit
Bit
Bit
Bit
Bit
7
7
0
0
0
SSTDR 3
SSTDR0
Bit
Bit
Bit
(LSB first transmission)
to
to
1
1
6
Bit
Bit
Bit
Bit
Bit
2
2
5
7
0
1 frame
SSTDR1
SSTDR0
SSTDR0
Bit
Bit
Bit
Bit
Bit
3
3
4
0
7
SSTDR2
SSTDR1
SSTXI interrupt generated
Bit
Bit
Bit
to
to
4
4
3
SSTXI interrupt
1 frame
Bit
Bit
Bit
Bit
Bit
5
5
2
7
0
generated
Bit
Bit
Bit
Bit
Bit
6
6
1
0
7
SSTXI interrupt generated
SSTDR1
Section 16 Synchronous Serial Communication Unit (SSU)
SSTDR2
1 frame
Bit
Bit
Bit
to
to
7
7
0
Bit
Bit
Bit
Bit
0
7
0
7
Data written to SSTDR0
SSTXI interrupt
Bit
Bit
Bit
Bit
1
6
0
7
SSTDR0
SSTDR3
generated
Bit
Bit
Bit
7
to
to
2
5
SSTXI interrupt generated
SSTDR0
SSTDR1
(MSB first transmission)
Bit
Bit
Bit
Bit
Bit
6
3
4
7
0
Rev. 3.00 Sep. 28, 2009 Page 815 of 1650
Bit
Bit
Bit
5
4
3
1 frame
SSTDR0
Bit
Bit
Bit
4
5
2
SSTXI interrupt generated
Bit
Bit
Bit
3
6
1
SSTXI interrupt
Bit
Bit
Bit
2
7
0
generated
Bit
1
Bit
0
REJ09B0313-0300