R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1313

Manufacturer Part Number

R0K572030S000BE

KIT DEV FOR SH7203

Manufacturer

Renesas Electronics America

Renesas Starter Kits (RSK)r

CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM

Silicon Manufacturer

Kit Contents

Silicon Family Name

Silicon Core Number

R5S72030W200FP

Tool / Board Applications

General Purpose MCU, MPU, DSP, DSC

Mcu Supported Families

Lead Free Status / RoHS Status

Contains lead / RoHS non-compliant

For Use With/related Products

Lead Free Status / Rohs Status

The display resolution is set up in LDHCNR, LDHSYNR, LDVDLNR, LDVTLNR, and

LDVSYNR. The LCD current-alternating period for an STN or DSTN display is set by using the

LDACLNR. The initial values in these registers are typical settings for VGA (640 × 480 dots) on

an STN or DSTN display.

The clock to be used is set with the LDICKR. The LCD module frame rate is determined by the

display interval + retrace line interval (non-display interval) for one screen set in a size related

This LCDC has a Vsync interrupt function so that it is possible to issue an interrupt at the

beginning of each vertical retrace line period (to be exact, at the beginning of the line after the last

line of the display). This function is set up by using the LDINTR.

An LCD module normally requires a specific sequence for processing to do with the cutoff of the

input power supply. Settings in LDPMMR, LDPSPR, and LDCNTR, in conjunction with the LCD

power-supply control pins (LCD_VCPWC, LCD_VEPWC, and LCD_DON), are used to provide

processing of power-supply control sequences that suits the requirements of the LCD module.

Figures 24.4 to 24.7 are summary timing charts for power-supply control sequences and table 24.6

is a summary of available power-supply control sequence periods.

Setting the Display Resolution

Power Management Registers

Rev. 3.00 Sep. 28, 2009 Page 1281 of 1650

Section 24 LCD Controller (LCDC)

REJ09B0313-0300