R0K572030S000BE Renesas Electronics America, R0K572030S000BE Datasheet - Page 1246

• Manufacturer Part Number: R0K572030S000BE
• Description: KIT DEV FOR SH7203
• Manufacturer: Renesas Electronics America
• Series: Renesas Starter Kits (RSK)r
• Type: MCUr

Specifications of R0K572030S000BE

• Contents: CPU Board, LCD Module, E10A-Lite Emulator, Cable, QuickStart Guide and CD-ROM
• Silicon Manufacturer: Renesas
• Kit Contents: Board
• Silicon Family Name: SH7203
• Silicon Core Number: R5S72030W200FP
• Tool / Board Applications: General Purpose MCU, MPU, DSP, DSC
• Mcu Supported Families: SH7203
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: SH7203
• Lead Free Status / Rohs Status: Compliant

Section 23 USB 2.0 Host/Function Module (USB)
For data transfers in the sending direction during high-speed operation, the PING packet is sent.
Control for the PING packet is done in the same manner as bulk transfers.
(c)
Zero-length packet data transfers are done in the direction opposite to that in the data stage. As
with the data stage, data transfers are done using the DCP buffer memory. Transactions are done
in the same manner as the data stage.
For the data packets of the status stage, the data PID must be transferred as DATA1. The data PID
should be set to DATA1 using the SQSET bit in DCPCFG.
For reception of a zero-length packet, the received data length must be confirmed using the DTLN
bits in CFIFOCTR after the BRDY interrupt is generated, and the buffer memory must then be
cleared using the BCLR bit in C/DnFIFOCTR.
For data transfers in the sending direction during high-speed operation, the PING packet is sent.
Control for the PING packet is done in the same manner as the bulk transfers.
(2)
(a)
This module always sends an ACK response in response to a setup packet that is normal with
respect to this module. The operation of this module operates in the setup stage is noted below.
1. When a new USB request is received, this module sets the following registers:
2. When a data packet is received right after the SETUP packet, the USB request parameters are
Response processing with respect to the control transfer should always be carried out after first
setting VALID = 0. In the VALID = 1 state, PID = BUF cannot be set, and the data stage cannot
be terminated.
Using the function of the VALID bit, this module is able to interrupt the processing of a request
currently being processed if a new USB request is received during a control transfer, and can send
a response in response to the newest request.
Rev. 3.00 Sep. 28, 2009 Page 1214 of 1650
REJ09B0313-0300
⎯ Set the VALID bit in INTSTS0 to 1.
⎯ Set the PID bit in DCPCTR to NAK.
⎯ Set the CCPL bit in DCPCTR to 0.
stored in USBREQ, USBVAL, USBINDX, and USBLENG.
Status Stage
Control Transfers when the Function Controller Function is Selected
Setup Stage